Efficient baseband design and implementation for high-throughput transmitters

Wireless communications are accelerating into the realm of higher data rates from hundreds of megabits to tens of gigabits per second. Increase in data rate requires higher throughput and higher utilization of spectral bandwidth. At the same time, we are seeing a demand for smaller chipsets with lower power budgets. Digital basebands with increased energy-efficiency are needed while fitting within tight area constraints. High spectral efficiency demands modulation schemes with high peak to average power ratio, increasing the precision requirements on the digital baseband circuitry. To enable a new class of energy-efficient millimeter wave communication systems based on outphasing power amplifiers (PAs), we have explored ways to implement high-throughput outphasing baseband functions with the smallest energy and area footprints. Aware of the limitations of field-programmable gate arrays (FPGA) in throughput and energy-efficiency, we have chosen to implement our digital baseband in application-specific integrated circuits to allow a truly integrated energy-efficient transmitter. By utilizing the changes in micro-architecture (parallelism and pipelining) and aggressive back-end power optimization techniques (noncritical path Vt replacement and sizing reductions), we achieve a record energy-efficiency and throughput for asymmetric-multilevel-outphasing (AMO) signal component separator (SCS) of 32pJ/sample at 0.6V supply voltage and 400Msamples/s, with an area of 0.41mm. For high-throughput area-constrained applications, our static random-access memories based AMO SCS design achieves 2× area reduction over the register-based design at the same throughput to allow more parallelism to meet the stringent throughput requirements. To compensate for system nonlinearity and memory effects, we implement a zeroavoidance shaping filter in place of the traditional shaping filter to improve convergence in model iterations of an outphasing transmitter, and design an energyand area-efficient digital predistorter (DPD). We use this DPD architecture to compensate for nonideal phase modulation, preamplifier saturation, and many transmitter nonidealities. Applying this developed methodology in spice-level simulation, we improve adjacent-channel-power-ratio (ACPR) of the outphasing Q-band 3 (45GHz) transmitter with 1.1Gsamples/s throughput from -30.6dB to -44.0dB and reduced error vector magnitude (EVM) from 4.5% down to 1.0% with 64-QuadratureAmplitude-Modulation (64QAM) and real-time zero avoidance. The energy efficiency of this predistorter at a throughput of 1.1Gsamples/s (3.3Gbps data rate with 64QAM modulation and oversampling ratio of 2) is 1.5nJ/sample. To illustrate the wide applicability of this proposed linearization methodology, we applied it to compensate for distortion in a radio-frequency PA. We apply the off-line iterative compensation method to a PA with 1.97GHz carrier frequency and 737Mbps data throughput with 64QAM. We map the designed DPD structure onto FPGAs with a utilization of 144 DSP slices and an energy efficiency of 1.7nJ/sample. To meet an ACPR constraint of -48dB, the uncompensated PA has to back-off the input power by 12dB with 3.3% power efficiency. The compensated PA has to back-off by only 6dB with 9.2% overall transmitter power efficiency which includes the DPD power, almost 3× the efficiency of uncompensated PA. Thesis Supervisor: Vladimir M. Stojanović Title: Associate Professor of Electrical Engineering and Computer Science